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features ? industry-standard architecture C emulates many 20-pin pals ? C low-cost, easy to use software tools ? high speed electrically-erasable pr ogrammable logic devices (ee pld) C 5ns maximum pin-to-pin delay ? low power, 100a pin controlled power-down mode option ? cmos and ttl compatible inputs and outputs C i/o pin keeper circuits ? advanced flash technology C reprogrammable C 100% tested ? high reliability cmos process C 20 year data retention C 100 erase/write cycles C2,000v esd protection C 200ma latchup immunity ? commercial and industrial temperature ranges ? dual-in-line and surface mount pa ckages in standard pinouts ? pci compliant ? green (rohs compliant) pa ckage options available description the atmel ? atf16v8c is a high performance eecmos programmable logic device (pld) that utilizes the atmel proven electrically-era sable (ee) flash memory technology. offered options include speeds down to 5ns and a 100a pin-controlled power-down mode. all speed ranges are specified over the full 5v 10% range for industrial temperature ranges, and 5v 5% for commercial range 5v devices. the atf16v8c incorporates a su perset of the generic architec tures, which allows direct replacement of the 16r8 family and most 20- pin combinatorial plds. eight outputs are each allocated eight product terms. three diffe rent modes of operation are configured auto- matically with software, and allow highly complex logic functions to be realized. the atf16v8c can significantly reduce total system power, thereby enhancing system reli- ability and reducing power supply costs. when pin 4 is configured as the power-down control pin, supply current drops to less than 100a whenever the pin is high. if the power- down feature isn't required for a particular app lication, pin 4 may be used as a logic input. also, the pin-keeper circuits eliminate the need for internal pull-up resistors along with their attendant power consumption. high performance electrically-erasable programmable logic devices atmel atf16v8c 0425h?pld?3/11
2 0425hCpldC3/11 atmel atf16v8c figure 0-1. block diagram note: 1. includes optional pd control pin figure 0-2. pin configurations pin name function clk clock i logic inputs i/o bidirectinoal buffers oe output enable v cc +5v supply pd power-down tssop top view dip/soic top view plcc top view 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 i/clk i1 i2 pd/i3 i4 i5 i6 i7 i8 gnd vcc i/o i/o i/o i/o i/o i/o i/o i/o i9/oe 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 i/clk i1 i2 pd/i3 i4 i5 i6 i7 i8 gnd vcc i/o i/o i/o i/o i/o i/o i/o i/o i9/oe 4 5 6 7 8 18 17 16 15 14 pd/i3 i4 i5 i6 i7 i/o i/o i/o i/o i/o 3 2 1 20 19 9 10 11 12 13 i8 gnd i9/oe i/o i/o i2 i1 i/clk vcc i/o
3 0425hCpldC3/11 atmel atf16v8c 1. absolute maximum ratings* 2. dc and ac characteristics table 2-1. dc and ac operating conditions note: 1. all i cc parameters measured with outputs open temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . -40 ? c to +85 ? c *notice: stresses beyond th ose listed unde r absolute maximum ratings may caus e permanent damage to the device. this is a stress rating only, and functional operation of the device at th ese or any other conditions beyond those indicated in the operational sections of this specification is not impl ied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. minimum voltage is -0.6v dc, which may undershoot to -2.0v for pulses of less than 20ns. maximum out- put pin voltage is v cc + 0.75v dc, which may overshoot to 7.0v for pulses of less than 20ns. storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-65 ? c to +150 ? c voltage on any pin with respect to ground . . . . . -2.0v to +7.0v (1) voltage on input pins with respect to ground during programming . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to +14.0v (1) programming voltage with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to +14.0v (1) commercial industrial operating temperature (ambient) 0 ? c - 70 ? c-40 ? c - 85 ? c v cc power supply 5v 5% 5v 10% table 2-2. dc characteristics symbol parameter condition min typ max units i il input or i/o low leakage current 0 ? v in ? v il (max) -10.0 a i ih input or i/o high leakage current 3.5 ? v in ? v cc 10.0 a i cc1 (1) power supply current, standby 15mhz, v cc = max, v in = 0, v cc , outputs open com. 115 ma ind. 130 ma i pd power supply current, power-down mode v cc = max, v in = 0, v cc com. 10 100 a ind. 10 105 a i os output short circuit current v out = 0.5v; v cc = 5v; t a = 25c -150 ma v il input low voltage min < v cc < max -0.5 0.8 v v ih input high voltage 2.0 v cc + 1 v v ol output low voltage v cc = min; all outputs i ol = 24ma com., ind. 0.5 v v oh output high voltage v cc = min i ol = -4.0ma 2.4 v i ol output lo w current v cc = min com. 24.0 ma ind. 12.0 ma i oh output high current v cc = min com., ind. -4.0 ma
4 0425hCpldC3/11 atmel atf16v8c figure 3. ac waveforms note: 1. timing measurement reference is 1.5v. input ac driv ing levels are 0.0v and 3.0v, unless otherwise specified. table 3-1. ac characteristics symbol parameter -5 -7 -10 units min max min max min max t pd input or feedback to non-registered output 1 5 3 7.5 3 10 ns t cf clock to feedback 3 3 6 ns t co clock to output 142527ns t s input or feedback setup time 3 5 7.5 ns t h input hold time 0 0 0 ns t p clock period 6 8 12 ns t w clock width 3 4 6 ns f max external feedback 1/(t s + t co ) 142 100 68 mhz internal feedback 1/(t s + t cf ) 166 125 74 mhz no feedback 1/(t p ) 166 125 83 mhz t ea input to output enable C product term 2 6 3 9 3 10 ns t er input to output disable C product term 2 5 2 9 2 10 ns t pzx oe pin to output enable 2 5 2 6 2 10 ns t pxz oe pin to output disable 1.5 5 1.5 6 1.5 10 ns
5 0425hCpldC3/11 atmel atf16v8c table 3-2. power-down ac characteristics (1)(2)(3) note: 1. output data is latched and held 2. hi-z outputs remain hi-z 3. clock and input transitions are ignored 4. input test waveforms and measurement levels: t r , t f < 1.5ns (10% to 90%) 5. output test loads 6. pin capacitance table 6-1. pin capacitance note: 1. typical values for nominal su pply voltage. this parameter is on ly sampled and is not 100% tested. symbol parameter -5 -7 -10 units min max min max min max t ivdh valid input before pd high 5.0 7.5 10 ns t gvdh valid oe before pd high 000ns t cvdh valid clock before pd high 000ns t dhix input dont care after pd high 5.0 7.5 10 ns t dhgx oe dont care after pd high 5.0 7.5 10 ns t dhcx clock dont care after pd high 5.0 7.5 10 ns t dliv pd low to valid input 5.0 7.5 10 ns t dlgv pd low to valid oe 15.0 20.0 25 ns t dlcv pd low to valid clock 15.0 20.0 25 ns t dlov pd low to valid output 20.0 25.0 30 ns output pin 5.0v cl = 50 pf r1 = 200 r2 = 200 typ max units conditions c in 58pfv in = 0v c out 68pfv out = 0v
6 0425hCpldC3/11 atmel atf16v8c 7. power-up reset registers of the atf16v8c are designed to reset duri ng power-up. at a point delayed slightly from v cc crossing v rst , all registers will be reset to the low state. as a result, the re gistered output state will always be high on power-up. this feature is critical for state machine initialization. howeve r, due to the asynchronous nature of reset and the uncertainty of how v cc actually rises in the system, the following conditions are required: 1. the v cc rise must be monotonic, from below 0.7v 2. after reset occurs, all input and fe edback setup times must be met befo re driving the clock term high, and 3. the signals from which the clock is derived must remain stable during t pr figure 8. power-up reset table 8-1. power-up reset parameters 9. power-down mode the atf16v8c includes an optional pi n controlled powerdown feature. device pin 4 may be configured as the power- down pin. when this feature is enabled and the power-down pin is high, total current cons umption drops to less than 100a. in the power-down mode, all outp ut data and internal logic states are latched and held. all registered and combinatorial output data remains valid. any outputs that were in a high-z state at the onset of power-down will remain at high-z. during power-down, all input signals except the power- down pin are blocked. the input and i/o pin-keeper circuits remain active to insure that pins do not float to indeterminate levels. this helps to further reduce system power. selection of the power-down opti on is specified in the atf16v8c logic design file. the logi c compiler will include this option selection in the otherwise standard 16v8 je dec fuse file. when the power-down featur e is not specified in the design file, pin 4 is available as a logic input, and there is no power-do wn pin. this allows the atf16v8c to be programmed using any existing standard 16v8 fuse file. note: some programmers list the jedec-compatible 16v8c (no pd used) separately from the no n-jedec compatib le 16v8cext. (ext for extended features.) 10. registered output preload registers of the atf16v8c are provided with circuitry to allow lo ading of each register with either a high or a low. this feature will simplify testing since any stat e can be forced into the registers to co ntrol test sequencing. a jedec file with preload is generated when a source file with vectors is comp iled. once downloaded, the jede c file preload sequence will be done automatically by approved programmers. parameter description typ max units t pr power-up reset time 600 1,000 ns v rst power-up reset voltage 3.8 4.5 v
7 0425hCpldC3/11 atmel atf16v8c 11. security fuse usage a single fuse is provided to prevent unauthorized copying of the atf16v8c fuse patterns. once programmed, fuse verify and preload are inhibited. however, the 64-bit user signature remains accessible. the security fuse will be programme d last, as its effect is immediate. 12. input and i/o pin-keeper circuits the atf16v8c contains internal input an d i/o pin-keeper circuits. these circuits allow each atf16v8c pin to hold its previous value even when it is not being driven by an extern al source or by the devices output buffer. this helps insure that all logic array inputs are at known, valid logic levels. th is reduces system power by prev enting pins from floating to indeterminate levels. by using pin-keeper ci rcuits rather than pull-up resistors, ther e is no dc current required to hold the pins in either logic state (high or low). these pin-keeper circuits are implemented as weak feedback inverters, as shown in the input diagram below. these keeper circuits can easily be overdriven by standard ttl- or cmos-compatible drivers. the typical overdrive current required is 40a. figure 13. input diagram figure 14. i/o diagram
8 0425hCpldC3/11 atmel atf16v8c 15. functional logic diagram description the logic option and functional diagrams describe the atf 16v8c architecture. eight configurable macrocells can be configured as a registered output, combinatorial i/o, combinatorial output, or dedicated input. the atf16v8c can be configured in one of three different modes. each mode makes the atf16v8c look like a different device. most pld compilers can choose the right mode automatically. the user can also force the selection by supplying the compiler with a mode selection. the determining factors would be the usage of register versus combinatorial outputs and dedicated outputs versus outp uts with output enable control. the atf16v8c universal architecture can be programmed to emulate many 20-pin pal devices. these architectural subsets can be found in each of the configuration modes de scribed in the following pages. the user can download the listed subset device jedec programming file to the pld prog rammer, and the atf16v8c can be configured to act like the chosen device. check with your progra mmer manufacturer for this capability. unused product terms are automatically disabled by the compil er to decrease power consumpt ion. a security fuse, when programmed, protects the content of the atf16v8c. eight bytes (64 fuses) of user signature are accessible to the user for purposes such as storing project name, part number, revision, or date. the user si gnature is accessible regardless of the state of the security fuse. table 15-1. compiler mode selection note: 1. please call atmel pld hotline at (408) 436-4333 for more information 2. only applicable for version 3.4 or lower 16. macrocell configuration software compilers support the three different omc modes as di fferent device types. these device types are listed in the table below. most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (oe ) usage. register usage on the device forces th e software to choose the registered mode. all combinatorial outputs with oe controlled by the product term will force th e software to choose the complex mode. the software will choose the simple mode only when all outputs are dedicated combinatorial without oe control. the different device types listed in the table can be us ed to override the automatic device select ion by the software. for further details, refer to the compiler software manuals. when using compiler software to configure the device, the user must pay special atte ntion to the following restrictions in each mode. in registered mode, pin 1 and pin 11 are permanently configured as clock and output enable, respectively. these pins cannot be configured as dedicate d inputs in the registered mode. in complex mode, pin 1 and pin 11 become dedicated inputs an d use the feedback paths of pin 19 and pin 12 respectively. because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode. registered complex simple auto select abel, atmel-abel p16v8r p16v8c p16v8as p16v8 with pd enable p16v8pdr (1) p16v8pdc (1) p16v8pd (1) p16v8pds (1) cupl, atmel-cupl g16v8ms g16v8ma g16v8as g16v8a with pd enable g16v8cpms g16v8cpma g16v8cpas g16v8cp log/ic gal16v8_r (2) gal16v8_c7 (2) gal16v8_c8 (2) gal16v8 orcad-pld registered complex simple gal16v8a pldesigner p16v8r p16v8c p16v8c p16v8a synario/atmel-synario na na na atf16v8c all with pd enable na na na atf16v8c (pd) all (1) tango-pld g16v8r g16v8c g16v8as g16v8
9 0425hCpldC3/11 atmel atf16v8c in simple mode, all feedback paths of the output pins are routed via the adjacent pins. in doing so, the two inner most pins (pins 15 and 16) will not have th e feedback option as these pi ns are always configured as dedicated combinatorial output. 16.1 atmel atf16v8c registered mode pal device emulation/pal replacement. the registered mode is used if one or more registers are required. each macrocell can be configured as either a registered or combinatoria l output or i/o, or as an input. for a registered output or i/o, the output is enabled by the oe pin, and the register is clocked by the cl k pin. eight product terms are allocated to the sum term. for a combinatorial output or i/o, the output enable is controlled by a product term, and seven product terms are allocated to the sum term. when the macrocell is configured as an in put, the output enable is permanently disabled. any register usage will make the compiler select this mode. the following registered devices can be emulated using this mode: 16r8 16rp8 16r6 16rp6 16r4 16rp4 figure 17. registered configuration for registered mode (1)(2) notes: 1. pin 1 controls common cl k for the regist ered outputs. pin 11 controls common oe for the registered outputs. pin 1 and pin 11 are permanently configured as clk and oe . 2. the development software configures all the architecture control bits and checks for proper pin usage automatically. figure 18. combinatorial configuration for registered mode (1)(2) notes: 1. pin 1 and pin 11 are perm anently configured as clk and oe . 2. the development software configures all the architecture control bits and checks for proper pin usage automatically.
10 0425hCpldC3/11 atmel atf16v8c figure 19. registered mode logic diagram note: * input not available if power-down mode is enabled
11 0425hCpldC3/11 atmel atf16v8c 20. atmel atf16v8c complex mode pal device emulation/pal replacement. in the complex mode, combinatorial ou tput and i/o functions are possible. pins 1 and 11 are regular inputs to the array. pins 13 through 18 have pin feedback paths back to the and-array, which makes full i/o capability possible. pins 12 and 19 (outermost macrocells) are outputs only. they do not have input capability. in this mode, each macrocell has seven product te rms going to the sum term and one product term enabling the output. combinatorial applications with an oe requirement will make the co mpiler select this mode. the following devices can be emulated using this mode: 16l8 16h8 16p8 figure 21. complex mode option 22. atmel atf16v8c simple mode pal device emulation/pal replacement. in the simple mode, eight product term s are allocated to the sum term. pins 15 and 16 (center macrocells) are permanently configured as comb inatorial outputs. other macrocells can be either inputs or combinatorial outputs with pin feedback to the and-array. pins 1 and 11 are regular inputs. the compiler selects this mode when a ll outputs are combinatorial without oe control. the following simple pals can be emulated using this mode: 10l8 10h8 10p8 12l6 12h6 12p6 14l4 14h4 14p4 16l2 16h2 16p2 figure 23. simple mode option 0 1
12 0425hCpldC3/11 atmel atf16v8c figure 24. complex mode logic diagram note: * input not available if power-down mode is enabled
13 0425hCpldC3/11 atmel atf16v8c note: simple mode logic diagram note: * input not available if power-down mode is enabled
14 0425hCpldC3/11 atmel atf16v8c
15 0425hCpldC3/11 atmel atf16v8c
16 0425hCpldC3/11 atmel atf16v8c
17 0425hCpldC3/11 atmel atf16v8c 25. ordering information using c product for industrial to use commercial product for industrial temperature rang es, down-grade one speed grade from the i to the c device (7ns c = 10ns i) and de-rate power by 30%. notes: 1. *shaded parts are being obsoleted in 2011 2. the suffix, u and x as part of the ordering cod e, implies the package is rohs compliant and lead free t pd (ns) t s (ns) t co (ns) atmel ordering code* package operation range 53 4 atf16v8c-5jx 20j commercial (0 ? c to 70 ? c) 7.5 5 5 ATF16V8C-7JU atf16v8c-7pu atf16v8c-7su 20j 20p3 20s industrial (-40 ? c to 85 ? c) 534 atf16v8c-5jc 20j commercial (0 ? c to 70 ? c) 7.5 5 5 atf16v8c-7jc atf16v8c-7pc atf16v8c-7sc atf16v8c-7xc 20j 20p3 20s 20x commercial (0 ? c to 70 ? c) atf16v8c-7ji atf16v8c-7pi atf16v8c-7si atf16v8c-7xi 20j 20p3 20s 20x industrial (-40 ? c to 85 ? c) 10 7.5 7 atf16v8c-10ji 20j industrial (-40 ? c to 85 ? c) package type 20j 20-lead, plastic j-leaded chip carrier (plcc) 20p3 20-lead, 0.300" wide, plastic dual inline package (pdip) 20s 20-lead, 0.300" wide, plastic gull-wing small outline (soic) 20x 20-lead, 4.4 mm wide, plastic thin shrink small outline (tssop)
18 0425hCpldC3/11 atmel atf16v8c 26. package drawings 20j C plcc 2325 orchard parkway san jose, ca 95131 r title drawing no. rev. notes: 1. this package conforms to jedec reference ms-018, variation aa. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 ? 4.572 a1 2.286 ? 3.048 a2 0.508 ? ? d 9.779 ? 10.033 d1 8.890 ? 9.042 note 2 e 9.779 ? 10.033 e1 8.890 ? 9.042 note 2 d2/e2 7.366 ? 8.382 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 20j , 20-lead, plastic j-leaded chip carrier (plcc) b 20j 10/04/01
19 0425hCpldC3/11 atmel atf16v8c 20p3 C pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20p3 , 20-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) d 20p3 1/23/04 pin 1 e1 a1 b e b1 c l seating plane a d e eb ec common dimensions (unit of measure = mm) symbol min nom max note a ? ? 5.334 a1 0.381 ? ? d 24.892 ? 26.924 note 2 e 7.620 ? 8.255 e1 6.096 ? 7.112 note 2 b 0.356 ? 0.559 b1 1.270 ? 1.551 l 2.921 ? 3.810 c 0.203 ? 0.356 eb ? ? 10.922 ec 0.000 ? 1.524 e 2.540 typ notes: 1. this package conforms to jedec reference ms-001, variation ad. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
20 0425hCpldC3/11 atmel atf16v8c 20s C soic
21 0425hCpldC3/11 atmel atf16v8c 20x C tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20x , (formerly 20t), 20-lead, 4.4 mm body width, plastic thin shrink small outline package (tssop) c 20x 10/23/03 6.60 (.260) 6.40 (.252) 1.20 (0.047) max 0.65 (.0256) bsc 0.20 (0.008) 0.09 (0.004) 0.15 (0.006) 0.05 (0.002) index mark 6.50 (0.256) 6.25 (0.246) seating plane 4.50 (0.177) 4.30 (0.169) pin 1 0.75 (0.030) 0.45 (0.018) 0o ~ 8o 0.30 (0.012) 0.19 (0.007) dimensions in millimeters and (inches). controlling dimension: millimeters. jedec standard mo-153 ac
22 0425hCpldC3/11 atmel atf16v8c 27. revision history doc. rev. date comments 0425h 03/2011 added green (rohs compli ant) package options removed lead based packaged from ordering section
atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: (+1) (408) 441-0311 fax: (+1) (408) 487-2600 www.atmel.com atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (+81) (3) 3523-3551 fax: (+81) (3) 3523-7581 ? 2011 atmel corporation. all rights reserved. / rev.: 0425hCpldC3/11 disclaimer: the information in this document is provided in connection with atmel prod ucts. no license, express or implied, by estoppel or otherwise, to any intellectual property right is gr anted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and conditions of sales located on the atmel website, atmel assumes no liabili ty whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not limited to, the impl ied warranty of merchantability, fitness for a particular purpo se, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including , without limitation, damages for loss and profits, business i nterruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. atmel does not make any commitment to upda te the information contained herein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products are not intended, authorized, or warranted for use as components in applica tions intended to support or sustain life. atmel ? , logo and combinations thereof, and others are registered tradem arks or trademarks of atmel corporation or its subsidiaries. o ther terms and product names may be trade- marks of others.

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